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DATE
2007
IEEE
99views Hardware» more  DATE 2007»
14 years 1 months ago
Instruction trace compression for rapid instruction cache simulation
Modern Application Specific Instruction Set Processors (ASIPs) have customizable caches, where the size, associativity and line size can all be customized to suit a particular ap...
Andhi Janapsatya, Aleksandar Ignjatovic, Sri Param...
ICMCS
2006
IEEE
117views Multimedia» more  ICMCS 2006»
14 years 1 months ago
Data Hiding for Speech Bandwidth Extension and its Hardware Implementation
Most of the current speech transmission systems are only able to deliver speech signals in a narrow frequency band. This narrowband speech is characterized by a thin and muffled ...
Fan Wu, Siyue Chen, Henry Leung
DATE
2008
IEEE
156views Hardware» more  DATE 2008»
14 years 2 months ago
Transparent Reconfigurable Acceleration for Heterogeneous Embedded Applications
Embedded systems are becoming increasingly complex. Besides the additional processing capabilities, they are characterized by high diversity of computational models coexisting in ...
Antonio Carlos Schneider Beck, Mateus B. Rutzig, G...
CAGD
2006
72views more  CAGD 2006»
13 years 7 months ago
Discrete one-forms on meshes and applications to 3D mesh parameterization
We describe how some simple properties of discrete one-forms directly relate to some old and new results concerning the parameterization of 3D mesh data. Our first result is an ea...
Steven J. Gortler, Craig Gotsman, Dylan Thurston
ICCAD
2005
IEEE
106views Hardware» more  ICCAD 2005»
14 years 4 months ago
New decompilation techniques for binary-level co-processor generation
—Existing ASIPs (application-specific instruction-set processors) and compiler-based co-processor synthesis approaches meet the increasing performance requirements of embedded ap...
Greg Stiff, Frank Vahid