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MICRO
2008
IEEE
106views Hardware» more  MICRO 2008»
14 years 2 months ago
EVAL: Utilizing processors with variation-induced timing errors
Parameter variation in integrated circuits causes sections of a chip to be slower than others. If, to prevent any resulting timing errors, we design processors for worst-case para...
Smruti R. Sarangi, Brian Greskamp, Abhishek Tiwari...
HPCA
2006
IEEE
14 years 8 months ago
A decoupled KILO-instruction processor
Building processors with large instruction windows has been proposed as a mechanism for overcoming the memory wall, but finding a feasible and implementable design has been an elu...
Miquel Pericàs, Adrián Cristal, Rube...
DATE
2006
IEEE
133views Hardware» more  DATE 2006»
14 years 1 months ago
Automatic generation of operation tables for fast exploration of bypasses in embedded processors
Customizing the bypasses in an embedded processor uncovers valuable trade-offs between the power, performance and the cost of the processor. Meaningful exploration of bypasses re...
Sanghyun Park, Eugene Earlie, Aviral Shrivastava, ...
IJHPCA
2008
75views more  IJHPCA 2008»
13 years 7 months ago
Towards Ultra-High Resolution Models of Climate and Weather
We present a speculative extrapolation of the performance aspects of an atmospheric general circulation model to ultra-high resolution and describe alternative technological paths...
Michael F. Wehner, Leonid Oliker, John Shalf
ISPASS
2005
IEEE
14 years 1 months ago
Partitioning Multi-Threaded Processors with a Large Number of Threads
Today’s general-purpose processors are increasingly using multithreading in order to better leverage the additional on-chip real estate available with each technology generation...
Ali El-Moursy, Rajeev Garg, David H. Albonesi, San...