In chip multiprocessors (CMPs), data accesslatency dependson the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access late...
With the growing number of programmable processing elements in today's MultiProcessor System-on-Chip (MPSoC) designs, the synergy required for the development of the hardware...
Lei Gao, Kingshuk Karuri, Stefan Kraemer, Rainer L...
In a Chip Multi-Processor (CMP) with private caches, the last level cache is statically partitioned between all the cores. This prevents such CMPs from sharing cache capacity in r...
The verification of an execution against memory consistency is known to be NP-hard. This paper proposes a novel fast memory consistency verification method by identifying a new na...
Yunji Chen, Yi Lv, Weiwu Hu, Tianshi Chen, Haihua ...
Multiple wireless technologies are converging to run on personal handhelds. The plethora of communication standards next to the cost issues of deeper submicron processing require ...
A. C. H. Ng, J. W. Weijers, Miguel Glassee, Thomas...