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ISPD
1998
ACM
244views Hardware» more  ISPD 1998»
14 years 7 days ago
Analysis, reduction and avoidance of crosstalk on VLSI chips
As chip size and design density increase, coupling effects (crosstalk) between signal wires become increasingly critical to on–chip timing and even functionality. A method is pr...
Tilmann Stöhr, Markus Alt, Asmus Hetzel, J&uu...
SDL
2003
147views Hardware» more  SDL 2003»
13 years 9 months ago
Modelling and Evaluation of a Network on Chip Architecture Using SDL
Network on Chip (NoC) is a new paradigm for designing large and complex systems on chips (SoCs). In this paradigm, a packet switched network is provided for on-chip communication. ...
Rickard Holsmark, Magnus Högberg, Shashi Kuma...
ENTCS
2008
83views more  ENTCS 2008»
13 years 8 months ago
Elastic Flow in an Application Specific Network-on-Chip
A Network-on-Chip (NoC) is increasingly needed to interconnect the large number and variety of Intellectual Property (IP) cells that make up a System-on-Chip (SoC). The network mu...
Daniel Gebhardt, Kenneth S. Stevens
HPCA
2003
IEEE
14 years 8 months ago
A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns
As the level of chip integration continues to advance at a fast pace, the desire for efficient interconnects-whether on-chip or off-chip--is rapidly increasing. Traditional interc...
Wai Hong Ho, Timothy Mark Pinkston
ICCD
2007
IEEE
139views Hardware» more  ICCD 2007»
14 years 5 months ago
Statistical simulation of chip multiprocessors running multi-program workloads
This paper explores statistical simulation as a fast simulation technique for driving chip multiprocessor (CMP) design space exploration. The idea of statistical simulation is to ...
Davy Genbrugge, Lieven Eeckhout