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TCAD
2008
93views more  TCAD 2008»
13 years 8 months ago
Chip Optimization Through STI-Stress-Aware Placement Perturbations and Fill Insertion
Starting at the 65-nm node, stress engineering to improve the performance of transistors has been a major industry focus. An intrinsic stress source--shallow trench isolation (STI)...
Andrew B. Kahng, Puneet Sharma, Rasit Onur Topalog...
ISCAS
2005
IEEE
173views Hardware» more  ISCAS 2005»
14 years 1 months ago
CMOS contact imager for monitoring cultured cells
— There is a growing interest in developing low cost, low power, highly integrated biosensor systems to characterize individual cells for applications such as cell analysis, drug...
Honghao Ji, Pamela Abshire, M. Urdaneta, Elisabeth...
CODES
2003
IEEE
14 years 1 months ago
Programmers' views of SoCs
System-on-chip (SoC) designs have the potential to change the way we organize computation. This potential has gone unrealized. Future SoCs will have multiple heterogeneous process...
JoAnn M. Paul
BMCBI
2008
148views more  BMCBI 2008»
13 years 8 months ago
Automating dChip: toward reproducible sharing of microarray data analysis
Background: During the past decade, many software packages have been developed for analysis and visualization of various types of microarrays. We have developed and maintained the...
Cheng Li
BMCBI
2006
128views more  BMCBI 2006»
13 years 8 months ago
Rank-statistics based enrichment-site prediction algorithm developed for chromatin immunoprecipitation on chip experiments
Background: High density oligonucleotide tiling arrays are an effective and powerful platform for conducting unbiased genome-wide studies. The ab initio probe selection method emp...
Srinka Ghosh, Heather A. Hirsch, Edward A. Sekinge...