Sciweavers

509 search results - page 52 / 102
» Chip Multi-Processor Generator
Sort
View
VLSID
2006
IEEE
144views VLSI» more  VLSID 2006»
14 years 8 months ago
A High-Performance VLSI Architecture for Advanced Encryption Standard (AES) Algorithm
In this paper we present a high-performance, high throughput, and area efficient architecture for the VLSI implementation of the AES algorithm. The subkeys, required for each round...
Naga M. Kosaraju, Murali R. Varanasi, Saraju P. Mo...
ICESS
2007
Springer
14 years 2 months ago
Memory Offset Assignment for DSPs
Compact code generation is very important for an embedded system that has to be implemented on a chip with a severely limited amount of size. Even though on-chip data memory optimi...
Jinpyo Hong, J. Ramanujam
ISCAS
2005
IEEE
275views Hardware» more  ISCAS 2005»
14 years 1 months ago
A low dropout, CMOS regulator with high PSR over wideband frequencies
Modern System-on-Chip (SoC) environments are swamped in high frequency noise that is generated by RF and digital circuits and propagated onto supply rails through capacitive coupli...
Vishal Gupta, Gabriel A. Rincón-Mora
ISCAS
2005
IEEE
192views Hardware» more  ISCAS 2005»
14 years 1 months ago
A sub-1V bandgap reference circuit using subthreshold current
— A bandgap reference circuit employing subthreshold current is proposed. Only a small fraction of VBE is utilized to generate the reference voltage of 170mV. Since the subthresh...
Hongchin Lin, Chao-Jui Liang
ASPDAC
2000
ACM
89views Hardware» more  ASPDAC 2000»
14 years 9 days ago
Circuit performance oriented device optimization using BSIM3 pre-silicon model parameters
We propose a circuit performance oriented device optimization methodology using pre-silicon parameters and critical paths which represent the performance of the chip. Based on our...
Mikako Miyama, Shiro Kamohara