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    IJNSEC
    2008
    106views more  IJNSEC 2008»
    Parallel Hardware Architectures for the Cryptographic Tate Pairing
    13 years 9 months ago
    Parallel Hardware Architectures for the Cryptographic Tate Pairing
    Download  ijns.femto.com.tw
    Identity-based cryptography uses pairing functions,which are sophisticated bilinear maps defined on elliptic curves.Computing pairings efficiently in software is presently a relev...
    Guido Marco Bertoni, Luca Breveglieri, Pasqualina ...
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    BMCBI
    2010
    143views more  BMCBI 2010»
    An efficient biological pathway layout algorithm combining grid-layout and spring embedder for complicated cellular location inf
    13 years 9 months ago
    An efficient biological pathway layout algorithm combining grid-layout and spring embedder for complicated cellular location inf
    Download  www.biomedcentral.com
    Background: Graph drawing is one of the important techniques for understanding biological regulations in a cell or among cells at the pathway level. Among many available layout al...
    Kaname Kojima, Masao Nagasaki, Satoru Miyano
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    TCC
    2009
    Springer
    184views Cryptology» more  TCC 2009»
    Secure Arithmetic Computation with No Honest Majority
    14 years 9 months ago
    Secure Arithmetic Computation with No Honest Majority
    Download  eprint.iacr.org
    We study the complexity of securely evaluating arithmetic circuits over finite rings. This question is motivated by natural secure computation tasks. Focusing mainly on the case o...
    Yuval Ishai, Manoj Prabhakaran, Amit Sahai
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    ISLPED
    2003
    ACM
    122views Hardware» more  ISLPED 2003»
    A mixed-clock issue queue design for globally asynchronous, locally synchronous processor cores
    14 years 2 months ago
    A mixed-clock issue queue design for globally asynchronous, locally synchronous processor cores
    Download  www.ece.cmu.edu
    Ever shrinking device sizes and innovative micro-architectural and circuit design techniques have made it possible to have multi-million transistor systems running at multi-gigahe...
    Venkata Syam P. Rapaka, Diana Marculescu
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    ISCAS
    2002
    IEEE
    153views Hardware» more  ISCAS 2002»
    Biological learning modeled in an adaptive floating-gate system
    14 years 2 months ago
    Biological learning modeled in an adaptive floating-gate system
    Download  users.ece.gatech.edu
    We have implemented an aspect of learning and memory in the nervous system using analog electronics. Using a simple synaptic circuit we realize networks with Hebbian type adaptati...
    Christal Gordon, Paul E. Hasler
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