253 search results - page 29 / 51 » Circuit partitions and |
VLSID
2001
IEEE
14 years 8 months ago
2001
IEEE
In this paper we describe a hardware design method for memory and register arrays that allows the application of formal equivalence checking for comparing a high-level register tr...
ICCSA
2005
Springer
14 years 1 months ago
2005
Springer
Abstract. In this paper, we present a parallel tabu search (TS) algorithm for efficient optimization of a constrained multiobjective VLSI standard cell placement problem. The prima...
DATE
2003
IEEE
14 years 1 months ago
2003
IEEE
We present a high-level synthesis algorithm solving the combined scheduling, allocation and binding problem minimizing area under both latency and maximum power per clock-cycle co...
FPGA
2005
ACM
14 years 1 months ago
2005
ACM
We present an automatic logic synthesis method targeted for highperformance asynchronous FPGA (AFPGA) architectures. Our method transforms sequential programs as well as high-leve...
DCC
2008
IEEE
14 years 7 months ago
2008
IEEE
We introduce an EDIF netlist graph algorithm which is lossy with respect to the original byte stream but lossless in terms of the circuit information it contains based on a graph ...