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    CF
    2005
    ACM
    124views Applied Computing» more  CF 2005»
    Drowsy region-based caches: minimizing both dynamic and static power dissipation
    13 years 9 months ago
    Drowsy region-based caches: minimizing both dynamic and static power dissipation
    Download  www.csl.cornell.edu
    Power consumption within the memory hierarchy grows in importance as on-chip data caches occupy increasingly greater die area. Among dynamic power conservation schemes, horizontal...
    Michael J. Geiger, Sally A. McKee, Gary S. Tyson
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    ISLPED
    2007
    ACM
    97views Hardware» more  ISLPED 2007»
    Detailed placement for leakage reduction using systematic through-pitch variation
    13 years 9 months ago
    Detailed placement for leakage reduction using systematic through-pitch variation
    Download  vlsicad.ucsd.edu
    We present a novel detailed placement technique that accounts for systematic through-pitch variations to reduce leakage. Leakage depends nearly exponentially on linewidth (gate le...
    Andrew B. Kahng, Swamy Muddu, Puneet Sharma
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    MCU
    1998
    154views Hardware» more  MCU 1998»
    A computation-universal two-dimensional 8-state triangular reversible cellular automaton
    13 years 9 months ago
    A computation-universal two-dimensional 8-state triangular reversible cellular automaton
    Download  www.iec.hiroshima-u.ac.jp
    A reversible cellular automaton (RCA) is a cellular automaton (CA) whose global function is injective and every configuration has at most one predecessor. Margolus showed that the...
    Katsunobu Imai, Kenichi Morita
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    TVLSI
    1998
    83views more  TVLSI 1998»
    Low overhead fault-tolerant FPGA systems
    13 years 7 months ago
    Low overhead fault-tolerant FPGA systems
    Download  www.cs.ucla.edu
    — Fault-tolerance is an important system metric for many operating environments, from automotive to space exploration. The conventional technique for improving system reliability...
    John Lach, William H. Mangione-Smith, Miodrag Potk...
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    ACSD
    2010
    IEEE
    239views Hardware» more  ACSD 2010»
    A Complete Synthesis Method for Block-Level Relaxation in Self-Timed Datapaths
    13 years 5 months ago
    A Complete Synthesis Method for Block-Level Relaxation in Self-Timed Datapaths
    Download  ftp.cs.man.ac.uk
    Self-timed circuits present an attractive solution to the problem of process variation. However, implementing selftimed combinational logic can be complex and expensive. This pape...
    W. B. Toms, David A. Edwards
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