253 search results - page 5 / 51 » Circuit partitions and |
ASPDAC
1999
ACM
14 years 2 days ago
1999
ACM
: This paper presents a method for evaluating an upper bound of simultaneous switching gates in combinational circuits. In this method, the original circuit is partitioned into sub...
DFT
2008
IEEE
14 years 2 months ago
2008
IEEE
The paper presents a new technique for designing a concurrently checking combinational circuit. The technique is based on partitioning the circuit into two independent sub-circuit...
IPPS
1998
IEEE
14 years 16 hour ago
1998
IEEE
In this communication Simulated Annealing and Genetic Algorithms, are applied to the graph partitioning problem. These techniques mimic processes in statistical mechanics and biol...
ASPDAC
1999
ACM
14 years 2 days ago
1999
ACM
In this paper, we present a fast and efficient Iterative Improvement Partitioning (IIP) technique for VLSI circuits and hybrid bucket structures on its implementation. Due to thei...
ICCD
1997
IEEE
13 years 12 months ago
1997
IEEE
Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a compute-intensive process. All previous work in parallel simulated annealing bas...