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» Circuit styles and strategies for CMOS VLSI design on SOI
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GLVLSI
2008
IEEE
120views VLSI» more  GLVLSI 2008»
14 years 2 months ago
SAT-based equivalence checking of threshold logic designs for nanotechnologies
Novel nano-scale devices have shown promising potential to overcome physical barriers faced by complementary metaloxide semiconductor (CMOS) technology in future circuit design. H...
Yexin Zheng, Michael S. Hsiao, Chao Huang
GLVLSI
2002
IEEE
106views VLSI» more  GLVLSI 2002»
14 years 29 days ago
A low power direct digital frequency synthesizer with 60 dBc spectral purity
We present a low-power sine-output Direct Digital Frequency Synthesizer (DDFS) realized in 0.18 µm CMOS that achieves 60 dBc spectral purity from DC to the Nyquist frequency. No ...
J. M. Pierre Langlois, Dhamin Al-Khalili
GLVLSI
2006
IEEE
110views VLSI» more  GLVLSI 2006»
14 years 2 months ago
Synthesis of a wideband low noise amplifier
Two generations of a wideband low noise amplifier (LNA) employing noise canceling principle have been synthesized. The first generation design was fabricated in a 0.35 µm SiGe Bi...
Abhishek Jajoo, Michael Sperling, Tamal Mukherjee
ISLPED
2003
ACM
85views Hardware» more  ISLPED 2003»
14 years 1 months ago
Energy recovery clocking scheme and flip-flops for ultra low-energy applications
A significant fraction of the total power in highly synchronous systems is dissipated over clock networks. Hence, low-power clocking schemes would be promising approaches for futu...
Matthew Cooke, Hamid Mahmoodi-Meimand, Kaushik Roy
DAC
2001
ACM
14 years 9 months ago
A True Single-Phase 8-bit Adiabatic Multiplier
This paper presents the design and evaluation of an 8-bit adiabatic multiplier. Both the multiplier core and its built-in self-test logic have been designed using a true single-ph...
Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthy...