3395 search results - page 568 / 679 » Circuit-aware architectural simulation |
VLSID
2004
IEEE
14 years 8 months ago
2004
IEEE
The detection of all open defects within 6T SRAM cells is always a challenge due to the significant test time requirements. This paper proposes a new design-for-test (DFT) techniq...
VLSID
2003
IEEE
14 years 8 months ago
2003
IEEE
In this paper we present statistical timing driven hMetisbased partitioning. We approach timing driven partitioning from a different perspective: we use the statistical timing cri...
VLSID
2003
IEEE
14 years 8 months ago
2003
IEEE
This paper quantifies the performance of typical functional unit interface designs in single-chip systems. We introduce a specific equation to guide the design of optimal module i...
VLSID
2003
IEEE
14 years 8 months ago
2003
IEEE
In the previous work, the problem of nding gate delays to eliminate glitches has been solved by linear programs (LP) requiring an exponentially large number ofconstraints. By intr...
VLSID
2002
IEEE
14 years 8 months ago
2002
IEEE
Predictive delay analysis is presented for a representative CMOS inverter with submicron device size using PREDICTMOS MOSFET model. As against SPICE, which adopts a time consuming...