3395 search results - page 99 / 679 » Circuit-aware architectural simulation |
147
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ICS
2000
Tsinghua U.
15 years 8 months ago
2000
Tsinghua U.
The rapid advancements of networking technology have boosted potential bandwidth to the point that the cabling is no longer the bottleneck. Rather, the bottlenecks lie at the cros...
144
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ECIR
2004
Springer
15 years 5 months ago
2004
Springer
We simulate different architectures of a distributed Information Retrieval system on a very large Web collection, in order to work out the optimal setting for a particular set of r...
179
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ISCA
2006
IEEE
15 years 4 months ago
2006
IEEE
Packet-based on-chip networks are increasingly being adopted in complex System-on-Chip (SoC) designs supporting numerous homogeneous and heterogeneous functional blocks. These Net...
138
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ERSA
2009
15 years 2 months ago
2009
In this paper, we introduce the Woolcano reconfigurable processor architecture. The architecture is based on the Xilinx Virtex-4 FX FPGA and leverages the Auxiliary Processing Uni...
105
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ISCA
1998
IEEE
15 years 8 months ago
1998
IEEE
Control-flow misprediction penalties are a major impediment to high performance in wide-issue superscalar processors. In this paper we present Selective Eager Execution (SEE), an ...