3 search results - page 1 / 1 » Circuit-level mismatch modelling and yield optimization for ... |
ICCD
2007
IEEE
14 years 1 months ago
2007
IEEE
A methodology for constructing circuit-level mismatch models and performing yield optimization is presented for CMOS analog circuits. The methodology combines statistical techniqu...
DATE
2005
IEEE
14 years 14 days ago
2005
IEEE
This paper suggests a practical “hybrid” synthesis methodology which integrates designer-derived analytical models for system-level description with simulation-based models at...
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
The scaling of CMOS technology into the nanometer era enables the fabrication of highly integrated systems, which increasingly contain analog and/or RF parts. However, scaling into...