197 search results - page 33 / 40 » Circuits, Pebbling and Expressibility |
GLVLSI
2009
IEEE
14 years 2 months ago
2009
IEEE
In the context of formal verification Bounded Model Checking (BMC) has shown to be very powerful for large industrial designs. BMC is used to check whether a circuit satisfies a...
SASP
2009
IEEE
14 years 2 months ago
2009
IEEE
Abstract—One of the ways that custom instruction set extensions can improve over software execution is through the use of hardware structures that have been optimized at the arit...
ASPDAC
2004
ACM
14 years 27 days ago
2004
ACM
- Under manufacturing process variation, a path through a fault site is called longest for delay test if there exists a process condition under which the path has the maximum delay...
DAC
2004
ACM
14 years 27 days ago
2004
ACM
Leakage current has become a stringent constraint in today’s processor designs in addition to traditional constraints on frequency. Since leakage current exhibits a strong inver...
CSCLP
2004
Springer
14 years 26 days ago
2004
Springer
We introduce a framework for studying and solving a class of CSP formulations. The framework allows constraints to be expressed as linear and nonlinear equations, then compiles th...