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» Clock Distribution Design in VLSI Circuits. An Overview
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ISPD
2003
ACM
110views Hardware» more  ISPD 2003»
14 years 3 months ago
Explicit gate delay model for timing evaluation
Delay evaluation is always a crucial concern in the VLSI design and it becomes increasingly more critical in the nowadays deep-submicron technology. To obtain an accurate delay va...
Muzhou Shao, Martin D. F. Wong, Huijing Cao, Youxi...
ISPD
2009
ACM
141views Hardware» more  ISPD 2009»
14 years 4 months ago
A faster approximation scheme for timing driven minimum cost layer assignment
As VLSI technology moves to the 65nm node and beyond, interconnect delay greatly limits the circuit performance. As a critical component in interconnect synthesis, layer assignmen...
Shiyan Hu, Zhuo Li, Charles J. Alpert
GLVLSI
2010
IEEE
190views VLSI» more  GLVLSI 2010»
13 years 11 months ago
A linear statistical analysis for full-chip leakage power with spatial correlation
In this paper, we present an approved linear-time algorithm for statistical leakage analysis in the present of any spatial correlation condition (strong or weak). The new algorith...
Ruijing Shen, Sheldon X.-D. Tan, Jinjun Xiong
VLSID
2008
IEEE
191views VLSI» more  VLSID 2008»
14 years 4 months ago
Programming and Performance Modelling of Automotive ECU Networks
The last decade has seen a phenomenal increase in the use of electronic components in automotive systems, resulting in the replacement of purely mechanical or hydraulic-implementa...
Samarjit Chakraborty, Sethu Ramesh
DAC
2007
ACM
14 years 10 months ago
Fast Second-Order Statistical Static Timing Analysis Using Parameter Dimension Reduction
The ability to account for the growing impacts of multiple process variations in modern technologies is becoming an integral part of nanometer VLSI design. Under the context of ti...
Zhuo Feng, Peng Li, Yaping Zhan