205 search results - page 40 / 41 » Clock gating architectures for FPGA power reduction |
DATE
2009
IEEE
14 years 4 months ago
2009
IEEE
— Today's innovations in the automotive sector are, to a great extent, based on electronics. The increasing integration complexity and stringent cost reduction goals turn E/...
NOCS
2009
IEEE
14 years 4 months ago
2009
IEEE
This paper presents a many-core heterogeneous computational platform that employs a GALS compatible circuit-switched on-chip network. The platform targets streaming DSP and embedd...
DSD
2002
IEEE
14 years 2 months ago
2002
IEEE
Continuing VLSI technology scaling raises several deep submicron (DSM) problems like relatively slow interconnect, power dissipation and distribution, and signal integrity. Those ...
TC
2008
13 years 9 months ago
2008
This paper examines the hardware implementation trade-offs when evaluating functions via piecewise polynomial approximations and interpolations for precisions of up to 24 bits. In ...
NIXDORF
1992
14 years 1 months ago
1992
We present some quantitative performance measurements for the computing power of Programmable Active Memories (PAM), as introduced by [2]. Based on Field Programmable Gate Array (...