96 search results - page 15 / 20 » Clock-Aware Placement for FPGAs |
IOLTS
2007
IEEE
14 years 1 months ago
2007
IEEE
i To boost logic density and reduce per unit power consumption SRAM-based FPGAs manufacturers adopted nanometric technologies. However, this technology is highly vulnerable to radi...
ISCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
– Increasing logic densities and clock frequencies on FPGAs lead to rapid increase in power density, which translates to higher on-chip temperature. In this paper, we investigate...
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
Approximate string matching problem is a common and often repeated task in information retrieval and bioinformatics. This paper proposes a generic design of a programmable array p...
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
Triple Modular Redundancy (TMR) is a suitable fault tolerant technique for SRAM-based FPGA. However, one of the main challenges in achieving 100% robustness in designs protected b...
DATE
2002
IEEE
14 years 10 days ago
2002
IEEE
We present an area and delay estimator in the context of a compiler that takes in high level signal and image processing applications described in MATLAB and performs automatic de...