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ISPD
1997
ACM
68views Hardware» more  ISPD 1997»
14 years 3 months ago
Closed form solution to simultaneous buffer insertion/sizing and wire sizing
In this paper, we consider the delay minimization problem of a wire by simultaneously considering bu er insertion, bu er sizing and wire sizing. We consider three versions of the ...
Chris C. N. Chu, D. F. Wong
ASPDAC
2006
ACM
176views Hardware» more  ASPDAC 2006»
14 years 2 months ago
Closed form solution for optimal buffer sizing using the Weierstrass elliptic function
Abstract-- This paper presents a fundamental result on buffer sizing. Given an interconnection wire with n buffers evenly spaced along the wire, we would like to size all buffers s...
Sebastian Vogel, Martin D. F. Wong
ISLPED
1996
ACM
72views Hardware» more  ISLPED 1996»
14 years 3 months ago
Simultaneous buffer and wire sizing for performance and power optimization
In this paper, we study the simultaneous buffer and wire sizing (SBWS) problem for delay and power dissipation minimization. We prove the BS/WS relation for optimal SBWS solutions...
Jason Cong, Cheng-Kok Koh, Kwok-Shing Leung
DATE
2002
IEEE
74views Hardware» more  DATE 2002»
14 years 3 months ago
Maze Routing with Buffer Insertion under Transition Time Constraints
In this paper, we address the problem of simultaneous routing and buffer insertion. Recently in [12, 22], the authors considered simultaneous maze routing and buffer insertion und...
Li-Da Huang, Minghorng Lai, D. F. Wong, Youxin Gao