Sciweavers

135 search results - page 26 / 27
» Code and Data Transformations for Improving Shared Cache Per...
Sort
View
121
Voted
ASAP
2007
IEEE
112views Hardware» more  ASAP 2007»
15 years 5 months ago
Scheduling Register-Allocated Codes in User-Guided High-Level Synthesis
In high-level synthesis, as for compilers, an important question is when register assignment should take place. Unlike compilers for which the processor architecture is given, syn...
Alain Darte, C. Quinson
126
Voted
ASAP
2008
IEEE
142views Hardware» more  ASAP 2008»
15 years 10 months ago
Managing multi-core soft-error reliability through utility-driven cross domain optimization
As semiconductor processing technology continues to scale down, managing reliability becomes an increasingly difficult challenge in high-performance microprocessor design. Transie...
Wangyuan Zhang, Tao Li
149
Voted
EUROPAR
2000
Springer
15 years 7 months ago
Design and Evaluation of a Compiler-Directed Collective I/O Technique
Abstract. Current approaches to parallel I/O demand extensive user effort to obtain acceptable performance. This is in part due to difficulties in understanding the characteristics...
Gokhan Memik, Mahmut T. Kandemir, Alok N. Choudhar...
135
Voted
ASPLOS
2010
ACM
15 years 10 months ago
MacroSS: macro-SIMDization of streaming applications
SIMD (Single Instruction, Multiple Data) engines are an essential part of the processors in various computing markets, from servers to the embedded domain. Although SIMD-enabled a...
Amir Hormati, Yoonseo Choi, Mark Woh, Manjunath Ku...
125
Voted
EP
1998
Springer
15 years 8 months ago
Memory Scalability in Constraint-Based Multimedia Style Sheet Systems
Abstract. Multimedia style sheet systems uniformly use a constraintbased model of layout. Constraints provide a uniform mechanism for all aspects of style management and layout and...
Terry Cumaranatunge, Ethan V. Munson