133 search results - page 1 / 27 » Code restructuring for improving cache performance of MPSoCs |
ICCAD
2005
IEEE
14 years 4 months ago
2005
IEEE
— One of the critical goals in code optimization for MPSoC architectures is to minimize the number of off-chip memory accesses. This is because such accesses can be extremely cos...
CODES
2011
IEEE
12 years 7 months ago
2011
IEEE
Two overriding concerns in the development of embedded MPSoCs are ease of programming and hardware complexity. In this paper we present SoC-TM, an integrated HW/SW solution for tr...
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
Utilizing on-chip caches in embedded multiprocessorsystem-on-a-chip (MPSoC) based systems is critical from both performance and power perspectives. While most of the prior work th...
CODES
2011
IEEE
12 years 7 months ago
2011
IEEE
Designing memory controllers for complex real-time and highperformance multi-processor systems-on-chip is challenging, since sufficient capacity and (real-time) performance must b...
CODES
2007
IEEE
14 years 1 months ago
2007
IEEE
3D stacked wafer integration has the potential to improve multiprocessor system-on-chip (MPSoC) integration density, performance, and power efficiency. However, the power density...