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FPL
2010
Springer
129views Hardware» more  FPL 2010»
13 years 6 months ago
FPGA Implementations of the Round Two SHA-3 Candidates
Abstract--The second round of the NIST-run public competition is underway to find a new hash algorithm(s) for inclusion in the NIST Secure Hash Standard (SHA-3). This paper present...
Brian Baldwin, Andrew Byrne, Liang Lu, Mark Hamilt...
WCET
2010
13 years 6 months ago
WCET Analysis of a Parallel 3D Multigrid Solver Executed on the MERASA Multi-Core
To meet performance requirements as well as constraints on cost and power consumption, future embedded systems will be designed with multi-core processors. However, the question o...
Christine Rochange, Armelle Bonenfant, Pascal Sain...
EUROSYS
2011
ACM
13 years 9 days ago
Increasing performance in byzantine fault-tolerant systems with on-demand replica consistency
Traditional agreement-based Byzantine fault-tolerant (BFT) systems process all requests on all replicas to ensure consistency. In addition to the overhead for BFT protocol and sta...
Tobias Distler, Rüdiger Kapitza
WMCSA
2012
IEEE
12 years 4 months ago
SpinLoc: spin once to know your location
The rapid growth of location-based applications has spurred extensive research on localization. Nonetheless, indoor localization remains an elusive problem mostly because the accu...
Souvik Sen, Romit Roy Choudhury, Srihari Nelakudit...
DAC
2001
ACM
14 years 9 months ago
A True Single-Phase 8-bit Adiabatic Multiplier
This paper presents the design and evaluation of an 8-bit adiabatic multiplier. Both the multiplier core and its built-in self-test logic have been designed using a true single-ph...
Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthy...