Network-on-Chip (NoC) architectures provide a scalable solution to the wire delay constraints in deep submicron VLSI designs. Recent research into the optimization of NoC architec...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
This paper proposes a test architecture aimed at reducing test time of distributed small embedded SRAMs (eSRAMs). This architecture improves the one proposed in [4, 5]. The improv...
In this paper we present a new variation of cultural probes, called Infrastructure Probes (IP). IPs can be seen as an additional ethnographic method to get a deeper understanding ...
Hybrid nanoelectronics are emerging as one viable option to sustain the Moore’s Law after the CMOS scaling limit is reached. One main design challenge in hybrid nanoelectronics ...
This invited talk starts out with a review of the previously developed Roomware® concept and sample prototypes as an approach for designing new forms of interaction and collaborat...