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» Communication Mechanisms for Parallel DSP Systems on a Chip
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MICRO
1992
IEEE
128views Hardware» more  MICRO 1992»
15 years 9 months ago
MISC: a Multiple Instruction Stream Computer
This paper describes a single chip Multiple Instruction Stream Computer (MISC) capable of extracting instruction level parallelism from a broad spectrum of programs. The MISC arch...
Gary S. Tyson, Matthew K. Farrens, Andrew R. Plesz...
CODES
2004
IEEE
15 years 9 months ago
Fast exploration of bus-based on-chip communication architectures
As a result of improvements in process technology, more and more components are being integrated into a single System-on-Chip (SoC) design. Communication between these components ...
Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdha...
CLUSTER
2002
IEEE
15 years 5 months ago
Open Metadata Formats: Efficient XML-Based Communication for High Performance Computing
High-performance computing faces considerable change as the Internet and the Grid mature. Applications that once were tightly-coupled and monolithic are now decentralized, with co...
Patrick Widener, Greg Eisenhauer, Karsten Schwan, ...
ACSC
2003
IEEE
15 years 11 months ago
Communication Performance Issues for Two Cluster Computers
Clusters of commodity machines have become a popular way of building cheap high performance parallel computers. Many of these designs rely on standard Ethernet networks as a syste...
Francis Vaughan, Duncan A. Grove, Paul D. Coddingt...
PVM
2010
Springer
15 years 4 months ago
PMI: A Scalable Parallel Process-Management Interface for Extreme-Scale Systems
Parallel programming models on large-scale systems require a scalable system for managing the processes that make up the execution of a parallel program. The process-management sys...
Pavan Balaji, Darius Buntinas, David Goodell, Will...