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136
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DATE
2003
IEEE
15 years 11 months ago
2003
IEEE
This paper describes a design methodology for the estimation of bus performance of a tuplespace for factory automation. The need of a tuplespace is motivated by the characteristic...
168
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CODES
2003
IEEE
15 years 11 months ago
2003
IEEE
In this paper, we are concerned about the performance estimation of bus-based architectures assuming that the task partitioning on the processing components is already determined....
129
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CODES
1999
IEEE
15 years 10 months ago
1999
IEEE
The power consumption due to the HW/SW communication on system-level buses represents one of the major contributions to the overall power budget. A model to estimate the switching...
170
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CASES
2005
ACM
15 years 7 months ago
2005
ACM
In this work, we propose and investigate the idea of enhancing a System-on-Chip (SoC) communication architecture (the fabric that integrates system components and carries the comm...
145
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HOTI
2008
IEEE
16 years 9 days ago
2008
IEEE
Buses have historically provided a flexible communications structure in computer systems. However, signal integrity constraints of high-speed electronics have made multi-drop elec...