37 search results - page 6 / 8 » Compact FPGA implementations of QUAD |
ASAP
2009
IEEE
14 years 2 months ago
2009
IEEE
—The Spectral Hash algorithm is one of the Round 1 candidates for the SHA-3 family, and is based on spectral arithmetic over a finite field, involving multidimensional discrete...
ACSD
2006
IEEE
14 years 1 months ago
2006
IEEE
An optimized functional design space exploration method for multimedia applications is proposed. The basis of the method is a way of representing the dependency and the concurrenc...
FPL
2005
Springer
14 years 1 months ago
2005
Springer
This paper presents an architecture and a synthesis method for programmable numerical function generators of trigonometric functions, logarithm functions, square root, reciprocal,...
ARC
2008
Springer
13 years 9 months ago
2008
Springer
Abstract. In this paper, we present the PARO design tool for the automated hardware synthesis of massively parallel embedded architectures for given dataflow dominant applications....
FPGA
2006
ACM
13 years 11 months ago
2006
ACM
Many System-on-a-Chip devices would benefit from the inclusion of reprogrammable logic on the silicon die, as it can add general computing ability, provide run-time reconfigurabil...