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ASPDAC
2005
ACM
107views Hardware» more  ASPDAC 2005»
13 years 9 months ago
Constraint extraction for pseudo-functional scan-based delay testing
Recent research results have shown that the traditional structural testing for delay and crosstalk faults may result in over-testing due to the non-trivial number of such faults t...
Yung-Chieh Lin, Feng Lu, Kai Yang, Kwang-Ting Chen...
ATS
2003
IEEE
131views Hardware» more  ATS 2003»
14 years 23 days ago
Software-Based Delay Fault Testing of Processor Cores
Software-based self-testing is a promising approach for the testing of processor cores which are embedded inside a System-on-a-Chip (SoC), as it can apply test vectors in function...
Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hi...
INFSOF
2011
176views more  INFSOF 2011»
13 years 2 months ago
Testing in Service Oriented Architectures with dynamic binding: A mapping study
Context: Service Oriented Architectures (SOA) have emerged as a new paradigm to develop interoperable and highly dynamic applications. Objective: This paper aims to identify the s...
Marcos Palacios, José García-Fanjul,...
VLSID
1996
IEEE
110views VLSI» more  VLSID 1996»
13 years 11 months ago
On test coverage of path delay faults
W epropose a coverage metric and a two-pass test generation method for path delay faults in combinational logic circuits. The coverage is measured for each line with a rising and ...
Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vi...
ICCAD
2000
IEEE
97views Hardware» more  ICCAD 2000»
13 years 12 months ago
Error Catch and Analysis for Semiconductor Memories Using March Tests
We present an error catch and analysis (ECA) system for semiconductor memories. The system consists of a test algorithm generator called TAGS, a fault simulator called RAMSES, and...
Chi-Feng Wu, Chih-Tsun Huang, Chih-Wea Wang, Kuo-L...