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DSN
2008
IEEE
14 years 2 months ago
Scheduling algorithms for unpredictably heterogeneous CMP architectures
In future large-scale multi-core microprocessors, hard errors and process variations will create dynamic heterogeneity, causing performance and power characteristics to differ amo...
Jonathan A. Winter, David H. Albonesi
ISCA
2007
IEEE
152views Hardware» more  ISCA 2007»
14 years 1 months ago
Carbon: architectural support for fine-grained parallelism on chip multiprocessors
Chip multiprocessors (CMPs) are now commonplace, and the number of cores on a CMP is likely to grow steadily. However, in order to harness the additional compute resources of a CM...
Sanjeev Kumar, Christopher J. Hughes, Anthony D. N...
JSA
2007
191views more  JSA 2007»
13 years 7 months ago
Automated memory-aware application distribution for Multi-processor System-on-Chips
Mapping of applications on a Multiprocessor System-on-Chip (MP-SoC) is a crucial step to optimize performance, energy and memory constraints at the same time. The problem is formu...
Heikki Orsila, Tero Kangas, Erno Salminen, Timo D....
DATE
2005
IEEE
135views Hardware» more  DATE 2005»
14 years 1 months ago
Compositional Memory Systems for Multimedia Communicating Tasks
Conventional cache models are not suited for real-time parallel processing because tasks may flush each other’s data out of the cache in an unpredictable manner. In this way th...
Anca Mariana Molnos, Marc J. M. Heijligers, Sorin ...
ASAP
2009
IEEE
144views Hardware» more  ASAP 2009»
14 years 4 months ago
Acceleration of Multiresolution Imaging Algorithms: A Comparative Study
—In this paper we consider a multiresolution filter and its realization on the Cell BE and GPUs. We not only present common and specific optimization strategies undertaken for ...
Richard Membarth, Philipp Kutzer, Hritam Dutta, Fr...