Sciweavers

622 search results - page 120 / 125
» Comparing the Optimal Performance of Multiprocessor Architec...
Sort
View
DAC
2008
ACM
14 years 8 months ago
ELIAD: efficient lithography aware detailed router with compact post-OPC printability prediction
In this paper, we present ELIAD, an efficient lithography aware detailed router to optimize silicon image after optical proximity correction (OPC) in a correct-by-construction man...
Minsik Cho, Kun Yuan, Yongchan Ban, David Z. Pan
MOBIHOC
2005
ACM
14 years 7 months ago
Interference-aware topology control and QoS routing in multi-channel wireless mesh networks
The throughput of wireless networks can be significantly improved by multi-channel communications compared with single-channel communications since the use of multiple channels ca...
Jian Tang, Guoliang Xue, Weiyi Zhang
ASPLOS
2012
ACM
12 years 3 months ago
Reflex: using low-power processors in smartphones without knowing them
To accomplish frequent, simple tasks with high efficiency, it is necessary to leverage low-power, microcontroller-like processors that are increasingly available on mobile systems...
Felix Xiaozhu Lin, Zhen Wang, Robert LiKamWa, Lin ...
FPL
2004
Springer
144views Hardware» more  FPL 2004»
13 years 11 months ago
A Methodology for Energy Efficient FPGA Designs Using Malleable Algorithms
A recent trend towards integrating FPGAs with many heterogeneous components, such as memory systems, dedicated multipliers, etc., has made them an attractive option for implementin...
Jingzhao Ou, Viktor K. Prasanna
GLVLSI
2007
IEEE
141views VLSI» more  GLVLSI 2007»
14 years 1 months ago
Transition-activity aware design of reduction-stages for parallel multipliers
We propose an interconnect reorganization algorithm for reduction stages in parallel multipliers. It aims at minimizing power consumption for given static probabilities at the pri...
Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Osc...