Sciweavers

622 search results - page 25 / 125
» Comparing the Optimal Performance of Multiprocessor Architec...
Sort
View
CODES
2007
IEEE
14 years 1 months ago
Reliable multiprocessor system-on-chip synthesis
This article presents a multiprocessor system-on-chip synthesis (MPSoC) algorithm that optimizes system mean time to failure. Given a set of directed acyclic periodic graphs of co...
Changyun Zhu, Zhenyu (Peter) Gu, Robert P. Dick, L...
CODES
2011
IEEE
12 years 7 months ago
Memory controllers for high-performance and real-time MPSoCs: requirements, architectures, and future trends
Designing memory controllers for complex real-time and highperformance multi-processor systems-on-chip is challenging, since sufficient capacity and (real-time) performance must b...
Benny Akesson, Po-Chun Huang, Fabien Clermidy, Den...
ISCA
2000
IEEE
91views Hardware» more  ISCA 2000»
13 years 11 months ago
Performance analysis of the Alpha 21264-based Compaq ES40 system
This paper evaluates performance characteristics of the Compaq ES40 shared memory multiprocessor. The ES40 system contains up to four Alpha 21264 CPU’s together with a high-perf...
Zarka Cvetanovic, Richard E. Kessler
ISCA
1993
IEEE
153views Hardware» more  ISCA 1993»
13 years 11 months ago
An Adaptive Cache Coherence Protocol Optimized for Migratory Sharing
Parallel programs that use critical sections and are executed on a shared-memory multiprocessor with a writeinvalidate protocol result in invalidation actions that could be elimin...
Per Stenström, Mats Brorsson, Lars Sandberg
LCTRTS
2010
Springer
13 years 5 months ago
Compiler directed network-on-chip reliability enhancement for chip multiprocessors
Chip multiprocessors (CMPs) are expected to be the building blocks for future computer systems. While architecting these emerging CMPs is a challenging problem on its own, program...
Ozcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin,...