Sciweavers

622 search results - page 77 / 125
» Comparing the Optimal Performance of Multiprocessor Architec...
Sort
View
COMSWARE
2007
IEEE
14 years 2 months ago
Leveraging MAC-layer information for single-hop wireless transport in the Cache and Forward Architecture of the Future Internet
— Cache and Forward (CNF) Architecture is a novel architecture aimed at delivering content efficiently to potentially large number of intermittently connected mobile hosts. It us...
Sumathi Gopal, Sanjoy Paul, Dipankar Raychaudhuri
HPCA
2009
IEEE
14 years 9 months ago
Adaptive Spill-Receive for robust high-performance caching in CMPs
In a Chip Multi-Processor (CMP) with private caches, the last level cache is statically partitioned between all the cores. This prevents such CMPs from sharing cache capacity in r...
Moinuddin K. Qureshi
CF
2009
ACM
14 years 3 months ago
Mapping the LU decomposition on a many-core architecture: challenges and solutions
Recently, multi-core architectures with alternative memory subsystem designs have emerged. Instead of using hardwaremanaged cache hierarchies, they employ software-managed embedde...
Ioannis E. Venetis, Guang R. Gao
ISCAS
2007
IEEE
161views Hardware» more  ISCAS 2007»
14 years 2 months ago
Hardware Architecture of a Parallel Pattern Matching Engine
Abstract— Several network security and QoS applications require detecting multiple string matches in the packet payload by comparing it against predefined pattern set. This proc...
Meeta Yadav, Ashwini Venkatachaliah, Paul D. Franz...
VLSID
2002
IEEE
116views VLSI» more  VLSID 2002»
14 years 9 months ago
Prioritized Prime Implicant Patterns Puzzle for Novel Logic Synthesis and Optimization
Compare CMOS Logic with Pass-Transistor Logic, a question was raised in our mind: "Does any rule exist that contains all good?" This paper reveals novel logic synthesis ...
Kuo-Hsing Cheng, Shun-Wen Cheng