1461 search results - page 31 / 293 » Comparing the Optimal Performance of Parallel Architectures |
ISCA
2007
IEEE
14 years 1 months ago
2007
IEEE
Chip multiprocessors (CMPs) are now commonplace, and the number of cores on a CMP is likely to grow steadily. However, in order to harness the additional compute resources of a CM...
PDP
2009
IEEE
14 years 2 months ago
2009
IEEE
Abstract—Execution of applications on upcoming highperformance computing (HPC) systems introduces a variety of new challenges and amplifies many existing ones. These systems will...
PLDI
1995
ACM
13 years 11 months ago
1995
ACM
Traditional list schedulers order instructions based on an optimistic estimate of the load latency imposed by the hardware and therefore cannot respond to variations in memory lat...
3DIC
2009
IEEE
14 years 15 days ago
2009
IEEE
Several forms of processor memory organizations have been in use to optimally access off-chip memory systems mainly the Hard disk drives (HDD). Recent trends show that the solid s...
ISPAN
1997
IEEE
13 years 11 months ago
1997
IEEE
The thesis of this research is that the task of exposing the parallelism in a given application should be left to the algorithm designer, who has intimate knowledge of the applica...