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» Compiled-code-based simulation with timing verification
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DAC
1999
ACM
13 years 12 months ago
Verification and Management of a Multimillion-Gate Embedded Core Design
Verification is one of the most critical and time-consuming tasks in today's design processes. This paper demonstrates the verification process of a 8.8 million gate design u...
Johann Notbauer, Thomas W. Albrecht, Georg Niedris...
DAC
2000
ACM
14 years 8 months ago
Symbolic timing simulation using cluster scheduling
We recently introduced symbolic timing simulation (STS) using data-dependent delays as a tool for verifying the timing of fullcustom transistor-level circuit designs, and for the ...
Clayton B. McDonald, Randal E. Bryant
VMCAI
2010
Springer
14 years 4 months ago
Complexity Bounds for the Verification of Real-Time Software
We present uniform approaches to establish complexity bounds for decision problems such as reachability and simulation, that arise naturally in the verification of timed software s...
Rohit Chadha, Axel Legay, Pavithra Prabhakar, Mahe...
DAC
1996
ACM
13 years 11 months ago
Innovative Verification Strategy Reduces Design Cycle Time for High-End Sparc Processor
Superscalar processor developers are creatively leveraging best-in-class design verification tools to meet narrow market windows. Accelerated simulation is especially useful owing...
Val Popescu, Bill McNamara
ISSS
2002
IEEE
120views Hardware» more  ISSS 2002»
14 years 13 days ago
Virtual Synchronization for Fast Distributed Cosimulation of Dataflow Task Graphs
Fast distributed cosimulation is a challenging problem for the embedded system design. The main theme of this paper is to increase simulation speed by reducing the frequency of in...
Soonhoi Ha, Sungchan Kim, Chan-Eun Rhee, Hyunguk J...