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DATE
2009
IEEE
189views Hardware» more  DATE 2009»
14 years 3 months ago
CUFFS: An instruction count based architectural framework for security of MPSoCs
—Multiprocessor System on Chip (MPSoC) architecture is rapidly gaining momentum for modern embedded devices. The vulnerabilities in software on MPSoCs are often exploited to caus...
Krutartha Patel, Sri Parameswaran, Roshan G. Ragel
CODES
2005
IEEE
14 years 2 months ago
Aggregating processor free time for energy reduction
Even after carefully tuning the memory characteristics to the application properties and the processor speed, during the execution of real applications there are times when the pr...
Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, ...
ERLANG
2004
ACM
14 years 2 months ago
HiPE on AMD64
Erlang is a concurrent functional language designed for developing large-scale, distributed, fault-tolerant systems. The primary implementation of the language is the Erlang/OTP s...
Daniel Luna, Mikael Pettersson, Konstantinos F. Sa...
HIPEAC
2010
Springer
14 years 5 months ago
Scalable Shared-Cache Management by Containing Thrashing Workloads
Abstract. Multi-core processors with shared last-level caches are vulnerable to performance inefficiencies and fairness issues when the cache is not carefully managed between the m...
Yuejian Xie, Gabriel H. Loh
DAC
1996
ACM
14 years 23 days ago
FADIC: Architectural Synthesis applied in IC Design
This paper discusses the design of a chip using architectural synthesis. The chip, FADIC, is applied in Digital Audio Broadcasting (DAB) receivers. It shows that architectural syn...
J. Huisken, F. Welten