39 search results - page 4 / 8 » Compiler Generated Multithreading to Alleviate Memory Latenc... |
ASPLOS
1992
ACM
13 years 11 months ago
1992
ACM
Software-controlled data prefetching is a promising technique for improving the performance of the memory subsystem to match today's high-performance processors. While prefet...
ASPLOS
1991
ACM
13 years 11 months ago
1991
ACM
Access/execute architectures have several advantages over more traditional architectures. Because address generation and memory access are decoupled from operand use, memory laten...
ISCA
2009
IEEE
14 years 2 months ago
2009
IEEE
Industry has shifted towards multi-core designs as we have hit the memory and power walls. However, single thread performance remains of paramount importance since some applicatio...
CODES
2005
IEEE
14 years 1 months ago
2005
IEEE
Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOM...
CGO
2008
IEEE
14 years 1 months ago
2008
IEEE
In this paper we investigate the benefit of scheduling non-critical loads for a higher latency during software pipelining. "Noncritical" denotes those loads that have s...