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MICRO
2007
IEEE
168views Hardware» more  MICRO 2007»
15 years 9 months ago
Global Multi-Threaded Instruction Scheduling
Recently, the microprocessor industry has moved toward chip multiprocessor (CMP) designs as a means of utilizing the increasing transistor counts in the face of physical and micro...
Guilherme Ottoni, David I. August
MICRO
2005
IEEE
136views Hardware» more  MICRO 2005»
15 years 9 months ago
Automatic Thread Extraction with Decoupled Software Pipelining
Until recently, a steadily rising clock rate and other uniprocessor microarchitectural improvements could be relied upon to consistently deliver increasing performance for a wide ...
Guilherme Ottoni, Ram Rangan, Adam Stoler, David I...
DAC
2006
ACM
16 years 4 months ago
Exploiting forwarding to improve data bandwidth of instruction-set extensions
Application-specific instruction-set extensions (custom instructions) help embedded processors achieve higher performance. Most custom instructions offering significant performanc...
Ramkumar Jayaseelan, Haibin Liu, Tulika Mitra
DELTA
2010
IEEE
15 years 8 months ago
Notations for Multiphase Pipelines
— FPGAs, (Field-Programmable Gate Arrays) are often used for embedded image processing applications. Parallelism, and in particular pipelining, is the most suitable architecture ...
Christopher T. Johnston, Donald G. Bailey, Paul J....
PPOPP
2003
ACM
15 years 8 months ago
Compiler support for speculative multithreading architecture with probabilistic points-to analysis
Speculative multithreading (SpMT) architecture can exploit thread-level parallelism that cannot be identified statically. Speedup can be obtained by speculatively executing threa...
Peng-Sheng Chen, Ming-Yu Hung, Yuan-Shin Hwang, Ro...