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» Compiler Technology for Two Novel Computer Architectures
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ASPLOS
2004
ACM
14 years 1 months ago
Compiler orchestrated prefetching via speculation and predication
This paper introduces a compiler-orchestrated prefetching system as a unified framework geared toward ameliorating the gap between processing speeds and memory access latencies. ...
Rodric M. Rabbah, Hariharan Sandanagobalane, Mongk...
PPOPP
2005
ACM
14 years 2 months ago
Exposing disk layout to compiler for reducing energy consumption of parallel disk based systems
Disk subsystem is known to be a major contributor to overall power consumption of high-end parallel systems. Past research proposed several architectural level techniques to reduc...
Seung Woo Son, Guangyu Chen, Mahmut T. Kandemir, A...
SAC
2006
ACM
14 years 2 months ago
A concurrent reactive Esterel processor based on multi-threading
Esterel is a concurrent synchronous language for developing reactive systems. As an alternative to the classical software and hardware synthesis paths, the reactive processing app...
Xin Li, Reinhard von Hanxleden
APCSAC
2005
IEEE
14 years 2 months ago
An Integrated Partitioning and Scheduling Based Branch Decoupling
Conditional branch induced control hazards cause significant performance loss in modern out-of-order superscalar processors. Dynamic branch prediction techniques help alleviate th...
Pramod Ramarao, Akhilesh Tyagi
ISQED
2006
IEEE
101views Hardware» more  ISQED 2006»
14 years 2 months ago
Compiler-Directed Power Density Reduction in NoC-Based Multi-Core Designs
As transistor counts keep increasing and clock frequencies rise, high power consumption is becoming one of the most important obstacles, preventing further scaling and performance...
Sri Hari Krishna Narayanan, Mahmut T. Kandemir, Oz...