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ITC
2003
IEEE
136views Hardware» more  ITC 2003»
14 years 27 days ago
Adapting JTAG for AC Interconnect Testing
The use of AC coupled interconnects to provide communication paths between devices is increasing. The existing IEEE 1149.1 boundary scan standard [1] (JTAG) has limitations that h...
Lee Whetsel
CGO
2005
IEEE
14 years 1 months ago
Maintaining Consistency and Bounding Capacity of Software Code Caches
Software code caches are becoming ubiquitous, in dynamic optimizers, runtime tool platforms, dynamic translators, fast simulators and emulators, and dynamic compilers. Caching fre...
Derek Bruening, Saman P. Amarasinghe
ICS
2001
Tsinghua U.
14 years 2 days ago
Multiplex: unifying conventional and speculative thread-level parallelism on a chip multiprocessor
Recent proposals for Chip Multiprocessors (CMPs) advocate speculative, or implicit, threading in which the hardware employs prediction to peel off instruction sequences (i.e., imp...
Chong-liang Ooi, Seon Wook Kim, Il Park, Rudolf Ei...
BMCBI
2008
125views more  BMCBI 2008»
13 years 7 months ago
XplorSeq: A software environment for integrated management and phylogenetic analysis of metagenomic sequence data
Background: Advances in automated DNA sequencing technology have accelerated the generation of metagenomic DNA sequences, especially environmental ribosomal RNA gene (rDNA) sequen...
Daniel N. Frank
ICCAD
2005
IEEE
147views Hardware» more  ICCAD 2005»
14 years 4 months ago
NoCEE: energy macro-model extraction methodology for network on chip routers
In this paper we present NoCEE, a fast and accurate method for extracting energy models for packet-switched Network on Chip (NoC) routers. Linear regression is used to model the r...
Jeremy Chan, Sri Parameswaran