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DATE
2007
IEEE
107views Hardware» more  DATE 2007»
14 years 2 months ago
Development of an ASIP enabling flows in ethernet access using a retargetable compilation flow
In this paper we research an FPGA based Application Specific Instruction Set Processor (ASIP) tailored to the needs of a flow aware Ethernet access node using a retargetable com...
K. Van Renterghem, P. Demuytere, Dieter Verhulst, ...
ICCD
1992
IEEE
124views Hardware» more  ICCD 1992»
13 years 11 months ago
The ETCA Data-Flow Functional Computer for Real-Time Image Processing
This paper presents a data- ow computer, constituted of a large array of data- ow processors and programmed using a functional language, and its application to realtime image proc...
Georges Quénot, Bertrand Zavidovique
CGO
2010
IEEE
14 years 2 months ago
Automated just-in-time compiler tuning
Managed runtime systems, such as a Java virtual machine (JVM), are complex pieces of software with many interacting components. The Just-In-Time (JIT) compiler is at the core of t...
Kenneth Hoste, Andy Georges, Lieven Eeckhout
ISSS
2002
IEEE
174views Hardware» more  ISSS 2002»
14 years 18 days ago
A Run-Time Word-Level Reconfigurable Coarse-Grain Functional Unit for a VLIW Processor
Nowadays, new DSP applications are offering combined and flexible multimedia and telecom services. VLIW processor architectures, which include dedicated but inflexible functional ...
Carles Rodoreda Sala, Natalino G. Busá
JRTIP
2007
108views more  JRTIP 2007»
13 years 7 months ago
Real-time hardware acceleration of the trace transform
The trace transform is a novel algorithm that has been shown to be effective in a number of image recognition tasks. It is a generalisation of the Radon transform that has been wid...
Suhaib A. Fahmy, Christos-Savvas Bouganis, Peter Y...