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IPPS
2009
IEEE
15 years 10 months ago
Exploiting DMA to enable non-blocking execution in Decoupled Threaded Architecture
DTA (Decoupled Threaded Architecture) is designed to exploit fine/medium grained Thread Level Parallelism (TLP) by using a distributed hardware scheduling unit and relying on exi...
Roberto Giorgi, Zdravko Popovic, Nikola Puzovic
DATE
2007
IEEE
114views Hardware» more  DATE 2007»
15 years 10 months ago
Mapping the physical layer of radio standards to multiprocessor architectures
We are concerned with the software implementation of baseband processing for the physical layer of radio standards (“Software Defined Radio - SDR”). Given the constraints for ...
Cyprian Grassmann, Mathias Richter, Mirko Sauerman...
FCCM
2007
IEEE
111views VLSI» more  FCCM 2007»
15 years 10 months ago
A Structural Object Programming Model, Architecture, Chip and Tools for Reconfigurable Computing
A new platform for reconfigurable computing has an object-based programming model, with architecture, silicon and tools designed to faithfully realize this model. The platform is ...
Michael Butts, Anthony Mark Jones, Paul Wasson
CC
2007
Springer
126views System Software» more  CC 2007»
15 years 10 months ago
An Array Allocation Scheme for Energy Reduction in Partitioned Memory Architectures
This paper presents a compiler technique that reduces the energy consumption of the memory subsystem, for an off-chip partitioned memory architecture having multiple memory banks ...
K. Shyam, R. Govindarajan
150
Voted
ISCA
2005
IEEE
134views Hardware» more  ISCA 2005»
15 years 9 months ago
An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors
Instruction set customization is an effective way to improve processor performance. Critical portions of application dataflow graphs are collapsed for accelerated execution on s...
Nathan Clark, Jason A. Blome, Michael L. Chu, Scot...