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ISCA
1998
IEEE
104views Hardware» more  ISCA 1998»
15 years 8 months ago
Selective Eager Execution on the PolyPath Architecture
Control-flow misprediction penalties are a major impediment to high performance in wide-issue superscalar processors. In this paper we present Selective Eager Execution (SEE), an ...
Artur Klauser, Abhijit Paithankar, Dirk Grunwald
IPPS
2008
IEEE
15 years 10 months ago
Reducing the run-time of MCMC programs by multithreading on SMP architectures
The increasing availability of multi-core and multiprocessor architectures provides new opportunities for improving the performance of many computer simulations. Markov Chain Mont...
Jonathan M. R. Byrd, Stephen A. Jarvis, A. H. Bhal...
132
Voted
ACSAC
2003
IEEE
15 years 9 months ago
MLS-PCA: A High Assurance Security Architecture for Future Avionics
1 DOD Joint Vision 2020 (JV2020) is the integrated multi-service planning document for conduct among coalition forces of future warfare. It requires the confluence of a number of k...
Clark Weissman
173
Voted
ICVS
2003
Springer
15 years 9 months ago
A Software Architecture for Distributed Visual Tracking in a Global Vision Localization System
The paper considers detecting and tracking multiple moving objects in real time by a multiagent active vision system. The main objective of the envisioned system is to maintain an ...
Sinisa Segvic, Slobodan Ribaric
120
Voted
IPPS
1994
IEEE
15 years 7 months ago
Building Multithreaded Architectures with Off-the-Shelf Microprocessors
Present-day parallel computers often face the problems of large software Overheadsfor process switching and interprocessor communication. These problems are addressed by the Multi...
Herbert H. J. Hum, Kevin B. Theobald, Guang R. Gao