931 search results - page 7 / 187 » Compiling for vector-thread architectures |
CGO
2006
IEEE
14 years 3 months ago
2006
IEEE
Explicit Data Graph Execution (EDGE) architectures offer the possibility of high instruction-level parallelism with energy efficiency. In EDGE architectures, the compiler breaks ...
DATE
1999
IEEE
14 years 2 months ago
1999
IEEE
We describe EXPRESSION, a language supporting architectural design space exploration for embedded Systems-onChip (SOC) and automatic generation of a retargetable compiler/simulato...
ASPLOS
1989
ACM
14 years 1 months ago
1989
ACM
A very long instruction word (VLIW) processorexploits parallelism by controlling multiple operations in a single instruction word. This paper describes the architecture and compil...
IEEEPACT
2002
IEEE
14 years 2 months ago
2002
IEEE
In this paper, we describe an algorithm and implementation of locality optimizations for architectures with instruction sets such as Intel’s SSE and Motorola’s AltiVec that su...
ICCAD
2005
IEEE
14 years 6 months ago
2005
IEEE
Many commercially available embedded processors are capable of extending their base instruction set for a specific domain of applications. While steady progress has been made in t...