Nanoscale crossbars built from nanowires can form high density memories and programmable logic devices. To integrate such nanoscale devices with other circuits, nanowire decoders ...
- The Cell Matrix Architecture is a massive array of dynamically self-configurable, uniformly connected, identical computational units. This architecture can enable efficient, prac...
In this paper, we present a VLSI architecture for separable 2-D Discrete Wavelet Transform (DWT). Based on 1-D DWT Recursive Pyramid Algorithm (RPA), a complete 2-D DWT output sch...
In this paper we present a single-chip FPGA full encryptor/decryptor core design of the AES algorithm. Our design performs all of them, encryption, decryption and key scheduling pr...
Ahead-of-Time and Just-in-Time compilation are common ways to improve runtime performances of restrained systems like Java Card by turning critical Java methods into native code. H...