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ET
1998
52views more  ET 1998»
15 years 3 months ago
Scalable Test Generators for High-Speed Datapath Circuits
This paper explores the design of efficient test sets and test-pattern generators for online BIST. The target applications are high-performance, scalable datapath circuits for whi...
Hussain Al-Asaad, John P. Hayes, Brian T. Murray
DATE
2008
IEEE
101views Hardware» more  DATE 2008»
15 years 10 months ago
A Game-Theoretic Approach to Real-Time System Testing
This paper presents a game-theoretic approach to the testing of uncontrollable real-time systems. By modelling the systems with Timed I/O Game Automata and specifying the test pur...
Alexandre David, Kim Guldstrand Larsen, Shuhao Li,...
MTDT
2000
IEEE
137views Hardware» more  MTDT 2000»
15 years 8 months ago
Diagnostic Testing of Embedded Memories Based on Output Tracing
A new approach to diagnostic testing of embedded memories is presented which enables the design of tests that provide complete detection and distinguishing of all faults in a give...
Dirk Niggemeyer, Elizabeth M. Rudnick, Michael Red...
ETS
2009
IEEE
128views Hardware» more  ETS 2009»
15 years 1 months ago
Algorithms for ADC Multi-site Test with Digital Input Stimulus
This paper reports two novel algorithms based on time-modulo reconstruction method intended for detection of the parametric faults in analogue-to-digital converters (ADC). In both ...
Xiaoqin Sheng, Hans G. Kerkhoff, Amir Zjajo, Guido...
ICCD
2006
IEEE
131views Hardware» more  ICCD 2006»
16 years 22 days ago
Power-Constrained SOC Test Schedules through Utilization of Functional Buses
— In this paper, we are proposing a core-based test methodology that utilizes the functional bus for test stimuli and response transportation. An efficient algorithm for the gen...
Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orail...