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» Completion Energies and Scale
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ICCAD
2002
IEEE
157views Hardware» more  ICCAD 2002»
14 years 5 months ago
Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads
Dynamic voltage scaling (DVS) reduces the power consumption of processors when peak performance is unnecessary. However, the achievable power savings by DVS alone is becoming limi...
Steven M. Martin, Krisztián Flautner, Trevo...
DATE
2006
IEEE
82views Hardware» more  DATE 2006»
14 years 3 months ago
Power-aware compilation for embedded processors with dynamic voltage scaling and adaptive body biasing capabilities
Traditionally, active power has been the primary source of power dissipation in CMOS designs. Although, leakage power is becoming increasingly more important as technology feature...
Po-Kuan Huang, Soheil Ghiasi
DATE
2003
IEEE
127views Hardware» more  DATE 2003»
14 years 2 months ago
Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology
In this paper we propose a design technique to pipeline cache memories for high bandwidth applications. With the scaling of technology cache access latencies are multiple clock cy...
Amit Agarwal, Kaushik Roy, T. N. Vijaykumar
CNSR
2004
IEEE
218views Communications» more  CNSR 2004»
14 years 20 days ago
CSN: A Network Protocol for Serving Dynamic Queries in Large-Scale Wireless Sensor Networks
A fundamental problem that confronts future applications of sensor networks is how to efficiently locate the sensor node that stores a particular data item. It is known that distr...
Muneeb Ali, Zartash Afzal Uzmi
ICPR
2008
IEEE
14 years 10 months ago
Object detection at multiple scales improves accuracy
For detecting objects in natural visual scenes, several powerful image features have been proposed which can collectively be described as spatial histograms of oriented energy. Th...
Stanley M. Bileschi