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VTS
2005
IEEE
106views Hardware» more  VTS 2005»
14 years 3 months ago
Segmented Addressable Scan Architecture
This paper presents a test architecture that addresses multiple problems faced in digital IC testing. These problems are test data volume, test application time, test power consum...
Ahmad A. Al-Yamani, Erik Chmelar, Mikhail Grinchuc...
IJCAI
2003
13 years 11 months ago
Multi-prototype Support Vector Machine
We extend multiclass SVM to multiple prototypes per class. For this framework, we give a compact constrained quadratic problem and we suggest an efficient algorithm for its optimi...
Fabio Aiolli, Alessandro Sperduti
CLOUDCOM
2010
Springer
13 years 7 months ago
Bag-of-Tasks Scheduling under Budget Constraints
Commercial cloud offerings, such as Amazon's EC2, let users allocate compute resources on demand, charging based on reserved time intervals. While this gives great flexibilit...
Ana-Maria Oprescu, Thilo Kielmann
VLSID
2005
IEEE
158views VLSI» more  VLSID 2005»
14 years 10 months ago
Algorithmic Implementation of Low-Power High Performance FIR Filtering IP Cores
This paper presents two schemes for the implementation of high performance and low power FIR filtering Intellectual Property (IP) cores. Low power is achieved through the utilizat...
C. H. Wang, Ahmet T. Erdogan, Tughrul Arslan
WABI
2001
Springer
138views Bioinformatics» more  WABI 2001»
14 years 2 months ago
Algorithms for Finding Gene Clusters
Abstract. Comparing gene orders in completely sequenced genomes is a standard approach to locate clusters of functionally associated genes. Often, gene orders are modeled as permut...
Steffen Heber, Jens Stoye