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ASPLOS
1992
ACM
13 years 11 months ago
Efficient Superscalar Performance Through Boosting
The foremost goal of superscalar processor design is to increase performance through the exploitation of instruction-level parallelism (ILP). Previous studies have shown that spec...
Michael D. Smith, Mark Horowitz, Monica S. Lam
MICRO
2002
IEEE
173views Hardware» more  MICRO 2002»
14 years 12 days ago
Vector vs. superscalar and VLIW architectures for embedded multimedia benchmarks
Multimedia processing on embedded devices requires an architecture that leads to high performance, low power consumption, reduced design complexity, and small code size. In this p...
Christoforos E. Kozyrakis, David A. Patterson
ICCD
2003
IEEE
104views Hardware» more  ICCD 2003»
14 years 4 months ago
On Reducing Register Pressure and Energy in Multiple-Banked Register Files
The storage for speculative values in superscalar processors is one of the main sources of complexity and power dissipation. In this paper, we present a novel technique to reduce ...
Jaume Abella, Antonio González
MICRO
2002
IEEE
118views Hardware» more  MICRO 2002»
14 years 12 days ago
Exploiting data-width locality to increase superscalar execution bandwidth
In a 64-bit processor, many of the data values actually used in computations require much narrower data-widths. In this study, we demonstrate that instruction data-widths exhibit ...
Gabriel H. Loh
ASYNC
2004
IEEE
78views Hardware» more  ASYNC 2004»
13 years 11 months ago
Hiding Synchronization Delays in a GALS Processor Microarchitecture
We analyze an Alpha 21264-like Globally
Greg Semeraro, David H. Albonesi, Grigorios Magkli...