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IEEEPACT
2005
IEEE
14 years 1 months ago
Dual-Core Execution: Building a Highly Scalable Single-Thread Instruction Window
Current integration trends embrace the prosperity of single-chip multi-core processors. Although multi-core processors deliver significantly improved system throughput, single-thr...
Huiyang Zhou
ASPDAC
2004
ACM
75views Hardware» more  ASPDAC 2004»
14 years 1 months ago
Power-performance trade-off using pipeline delays
— We study the delays faced by instructions in the pipeline of a superscalar processor and its impact on power and performance. Instructions that are ready-on-dispatch (ROD) are ...
G. Surendra, Subhasis Banerjee, S. K. Nandy
ISCA
2003
IEEE
96views Hardware» more  ISCA 2003»
14 years 25 days ago
Parallelism in the Front-End
As processor back-ends get more aggressive, front-ends will have to scale as well. Although the back-ends of superscalar processors have continued to become more parallel, the fro...
Paramjit S. Oberoi, Gurindar S. Sohi
MICRO
1993
IEEE
128views Hardware» more  MICRO 1993»
13 years 11 months ago
Techniques for extracting instruction level parallelism on MIMD architectures
Extensive research has been done on extracting parallelism from single instruction stream processors. This paper presents some results of our investigation into ways to modify MIM...
Gary S. Tyson, Matthew K. Farrens
ISCA
1995
IEEE
110views Hardware» more  ISCA 1995»
13 years 11 months ago
Instruction Cache Fetch Policies for Speculative Execution
Current trends in processor design are pointing to deeper and wider pipelines and superscalar architectures. The efficient use of these resources requires speculative execution, ...
Dennis Lee, Jean-Loup Baer, Brad Calder, Dirk Grun...