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ASYNC
2002
IEEE
120views Hardware» more  ASYNC 2002»
14 years 2 months ago
Relative Timing Based Verification of Timed Circuits and Systems
Advanced clock-delayed1 and self-resetting domino circuits are becoming increasingly important design styles in aggressive synchronous as well as asynchronous design. Their design...
Peter A. Beerel, Ken S. Stevens, Hoshik Kim
DATE
2008
IEEE
106views Hardware» more  DATE 2008»
14 years 4 months ago
Modeling Event Stream Hierarchies with Hierarchical Event Models
Compositional Scheduling Analysis couples local scheduling analysis via event streams. While local analysis has successfully been extended to include hierarchical scheduling strat...
Jonas Rox, Rolf Ernst
DATE
2009
IEEE
126views Hardware» more  DATE 2009»
14 years 4 months ago
On hierarchical statistical static timing analysis
— Statistical static timing analysis deals with the increasing variations in manufacturing processes to reduce the pessimism in the worst case timing analysis. Because of the cor...
Bing Li, Ning Chen, Manuel Schmidt, Walter Schneid...
TII
2011
206views Education» more  TII 2011»
13 years 4 months ago
Timing-Failure Risk Assessment of UML Design Using Time Petri Net Bound Techniques
Abstract—Software systems that do not meet their timing constraints can cause risks. In this work, we propose a comprehensive method for assessing the risk of timing failure by e...
Simona Bernardi, Javier Campos, José Merseg...
FORTE
1997
13 years 11 months ago
On-Line Timed Protocol Trace Analysis Based on Uncertain State Descriptions
This paper presents a new approach to the task of passive protocol tracing. The method called FollowSM for the first time meets all requirements of practical in-field use, inclu...
Marek Musial