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HPCA
2009
IEEE
14 years 8 months ago
Prediction router: Yet another low latency on-chip router architecture
Network-on-Chips (NoCs) are quite latency sensitive, since their communication latency strongly affects the application performance on recent many-core architectures. To reduce th...
Hiroki Matsutani, Michihiro Koibuchi, Hideharu Ama...
AINA
2005
IEEE
14 years 29 days ago
CAM-Based Huffman Decoding Made Power Efficient
Ternary content addressable (TCAM) is favorable for high-speed search due to its parallel architecture and ability for searching arbitrary-length keys. However, the usage of TCAM ...
Pi-Chung Wang, Chun-Liang Lee, Yuan-Rung Yang, Hun...
MICRO
2010
IEEE
153views Hardware» more  MICRO 2010»
13 years 5 months ago
Throughput-Effective On-Chip Networks for Manycore Accelerators
As the number of cores and threads in manycore compute accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnection network des...
Ali Bakhoda, John Kim, Tor M. Aamodt
TPDS
2008
96views more  TPDS 2008»
13 years 7 months ago
Stochastic Graph Processes for Performance Evaluation of Content Delivery Applications in Overlay Networks
This paper proposes a new methodology to model the distribution of finite size content to a group of users connected through an overlay network. Our methodology describes the distr...
Damiano Carra, Renato Lo Cigno, Ernst W. Biersack
HPCA
2003
IEEE
14 years 7 months ago
A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns
As the level of chip integration continues to advance at a fast pace, the desire for efficient interconnects-whether on-chip or off-chip--is rapidly increasing. Traditional interc...
Wai Hong Ho, Timothy Mark Pinkston